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Disambiguation of "Shafaei, Alireza"

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An efficient timing analysis model for 6T FinFET SRAM using current-based method.

, , , , and . ISQED, page 263-268. IEEE, (2016)

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Mohsen Shafaei

Shahram Shafaei

Alireza Djirsarai

Alireza Azem

Alireza Rahimi

 

Other publications of authors with the same name

Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework., , and . DAC, page 107:1-107:6. ACM, (2016)Design of a universal logic block for fault-tolerant realization of any logic operation in trapped-ion quantum circuits., , , and . Quantum Inf. Process., 13 (5): 1267-1299 (2014)A thermally-aware energy minimization methodology for global interconnects., , , and . DATE, page 1213-1218. IEEE, (2017)Reversible logic synthesis of k-input, m-output lookup tables., , and . DATE, page 1235-1240. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement., , and . DATE, page 1465-1468. IEEE, (2018)Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write Assist Circuitry., , and . ACM Great Lakes Symposium on VLSI, page 415-420. ACM, (2016)A Less Biased Evaluation of Out-of-distribution Sample Detectors., , and . BMVC, page 3. BMVA Press, (2019)Low write-energy STT-MRAMs using FinFET-based access transistors., , and . ICCD, page 374-379. IEEE Computer Society, (2014)A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cell., , and . ISQED, page 280-285. IEEE, (2018)Cofactor Sharing for Reversible Logic Synthesis., , and . ACM J. Emerg. Technol. Comput. Syst., 11 (2): 14:1-14:21 (2014)