Author of the publication

Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation.

, , , , and . ISQED, page 139-146. IEEE, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Nalam, Satyanand
add a person with the name Nalam, Satyanand
 

Other publications of authors with the same name

Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers., , , and . DAC, page 138-143. ACM, (2010)Analyzing static and dynamic write margin for nanometer SRAMs., , and . ISLPED, page 129-134. ACM, (2008)Improving SRAM Vmin and yield by using variation-aware BTI stress., , , , , and . CICC, page 1-4. IEEE, (2010)Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation., , , , and . ISQED, page 139-146. IEEE, (2010)Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T., and . CICC, page 709-712. IEEE, (2009)17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology., , , , , , and . ISSCC, page 308-309. IEEE, (2016)17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 23.6Mb/mm2 SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications., , , , , and . ISSCC, page 196-198. IEEE, (2018)5T SRAM With Asymmetric Sizing for Improved Read Stability., and . IEEE J. Solid State Circuits, 46 (10): 2431-2442 (2011)Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories., , and . VLSI Design, page 139-144. IEEE Computer Society, (2014)