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Disambiguation of "Barraud, Sylvain"

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Statistical characterization of drain current local and global variability in sub 15nm Si/SiGe Trigate pMOSFETs.

, , , , , and . ESSDERC, page 142-145. IEEE, (2016)

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Sylvain Broyer

Sylvain Mogliacci

Sylvain Marlière

Sylvain Jay

Sylvain Didelot

 

Other publications of authors with the same name

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors., , , , , and . ESSDERC, page 223-226. IEEE, (2021)Si MOS technology for spin-based quantum computing., , , , , , , , , and 7 other author(s). ESSDERC, page 12-17. IEEE, (2018)Statistical characterization of drain current local and global variability in sub 15nm Si/SiGe Trigate pMOSFETs., , , , , and . ESSDERC, page 142-145. IEEE, (2016)Towards scalable silicon quantum computing., , , , , , , , , and 7 other author(s). DRC, page 1-2. IEEE, (2018)Analog performance of strained SOI nanowires down to 10K., , , , , , and . ESSDERC, page 222-225. IEEE, (2016)Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs., , , , , and . Microelectron. Reliab., 51 (5): 885-888 (2011)Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors., , , and . ESSDERC, page 194-197. IEEE, (2019)Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs., , , , , , and . ESSDERC, page 300-303. IEEE, (2013)Performance & reliability of 3D architectures (πfet, Finfet, Ωfet)., , , , , , , , , and . IRPS, page 6. IEEE, (2018)Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities., , , , , , , , , and 6 other author(s). ESSDERC, page 121-124. IEEE, (2012)