Author of the publication

On-chip memory efficient data layout for 2D FFT on 3D memory integrated FPGA.

, , and . HPEC, page 1-7. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

OSCAR: Optimizing SCrAtchpad reuse for graph processing., , , and . HPEC, page 1-7. IEEE, (2017)ReCALL: Reordered Cache Aware Locality Based Graph Processing., , , and . HiPC, page 273-282. IEEE Computer Society, (2017)FPGA-Based Acceleration of Pattern Matching in YARA., , , , , and . ARC, volume 9625 of Lecture Notes in Computer Science, page 320-327. Springer, (2016)Towards Performance Modeling of 3D Memory Integrated FPGA Architectures., , and . ARC, volume 9040 of Lecture Notes in Computer Science, page 443-450. Springer, (2015)Optimal data layout for block-level random accesses to scratchpad., , and . HPEC, page 1-7. IEEE, (2017)Optimal Dynamic Data Layouts for 2D FFT on 3D Memory Integrated FPGA., , and . PaCT, volume 9251 of Lecture Notes in Computer Science, page 338-348. Springer, (2015)Energy performance of FPGAs on PERFECT suite kernels., , , , , , , , and . HPEC, page 1-6. IEEE, (2014)On-chip memory efficient data layout for 2D FFT on 3D memory integrated FPGA., , and . HPEC, page 1-7. IEEE, (2016)Optimal dynamic data layouts for 2D FFT on 3D memory integrated FPGA., , and . J. Supercomput., 73 (2): 652-663 (2017)High-performance packet classification on GPU., , and . HPEC, page 1-6. IEEE, (2014)