( en | de | ru )

 

Disambiguation of "Katsuragi, Makihiko"

Author of the publication

copydeleteadd this publication to your clipboard
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB.

, , , , , , , , and . IEEE J. Solid State Circuits, 51 (7): 1630-1640 (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Katsuragi, Makihiko
add a person with the name Katsuragi, Makihiko
 

Other publications of authors with the same name

A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique., , , , , and . ASP-DAC, page 5-6. IEEE, (2016)A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB., , , , , , , , and . ESSCIRC, page 380-383. IEEE, (2015)A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB., , , , , , , , and . IEEE J. Solid State Circuits, 51 (7): 1630-1640 (2016)A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad., , , , , , , and . IEEE J. Solid State Circuits, 51 (5): 1246-1260 (2016)A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 54 (5): 1375-1390 (2019)A 28.16-Gb/s Area-Efficient 60GHz CMOS Bi-Directional Transceiver for IEEE 802.11ay., , , , , , , , , and 3 other author(s). A-SSCC, page 77-78. IEEE, (2018)A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 54 (5): 1363-1374 (2019)