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A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB.

, , , , , , , , and . IEEE J. Solid State Circuits, 51 (7): 1630-1640 (2016)

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GPU-based first aid for system faults., and . APSys, page 38-45. ACM, (2022)A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB., , , , , , , , and . ESSCIRC, page 380-383. IEEE, (2015)A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture., , , , , , , , , and . IEEE J. Solid State Circuits, 51 (6): 1385-1397 (2016)Maximum Number of Steps of Topswops on 18 and 19 Cards., , , and . CoRR, (2021)25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation., , , , , , , , , and 5 other author(s). A-SSCC, page 109-112. IEEE, (2016)A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection., , , , , , and . ASP-DAC, page 42-43. IEEE, (2015)Escape from the Room., , and . COCOON, volume 13595 of Lecture Notes in Computer Science, page 232-241. Springer, (2022)A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz., , , , and . ESSCIRC, page 343-346. IEEE, (2014)A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB., , , , , , , , and . IEEE J. Solid State Circuits, 51 (7): 1630-1640 (2016)