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Accelerating Apache Spark with FPGAs., and . Concurr. Comput. Pract. Exp., (2019)The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning., , , and . Int. J. Parallel Program., 27 (5): 327-356 (1999)Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding., , and . Inf. Process. Manag., 30 (6): 805-816 (1994)A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center., , , and . FPGA, page 262-271. ACM, (2019)Optimization of data prefetch helper threads with path-expression based statistical modeling., and . ICS, page 210-221. ACM, (2007)Virtualized Reconfigurable Hardware Resources in the SAVI Testbed., , , , and . TRIDENTCOM, volume 137 of Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, page 54-64. Springer, (2014)An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC., , and . FPT, page 123-130. IEEE, (2014)Exploring pipe implementations using an OpenCL framework for FPGAs., and . FPT, page 112-119. IEEE, (2015)A high-performance architecture for training Viola-Jones object detectors., and . FPT, page 174-181. IEEE, (2012)Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks., , , , , and . FPT, page 265-268. IEEE, (2016)