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A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.

B. Keller, M. Cochet, B. Zimmer, J. Kwak, A. Puggelli, Y. Lee, M. Blagojevic, S. Bailey, P. Chiu, P. Dabbelt, C. Schmidt, E. Alon, K. Asanovic, and B. Nikolic. IEEE J. Solid State Circuits, 52 (7): 1863-1875 (2017)

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Christopher Bailey

Paul Bailey

Sam Bailey

Jörg Schmidt-Bailey

Other publications of authors with the same name

Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors.R. Jevtic, H. Le, M. Blagojevic, S. Bailey, K. Asanovic, E. Alon, and B. Nikolic. IEEE Trans. Very Large Scale Integr. Syst., 23 (4): 723-730 (2015)A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.A. Wang, W. Bae, J. Han, S. Bailey, P. Rigge, O. Ocal, Z. Wang, K. Ramchandran, E. Alon, and B. Nikolic. ESSCIRC, page 322-325. IEEE, (2018)A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET.A. Wang, B. Richards, D. Dabbelt, H. Mao, S. Bailey, J. Han, E. Chang, J. Dunn, E. Alon, and B. Nikolic. A-SSCC, page 305-308. IEEE, (2017)A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.A. Wang, W. Bae, J. Han, S. Bailey, O. Ocal, P. Rigge, Z. Wang, K. Ramchandran, E. Alon, and B. Nikolic. IEEE J. Solid State Circuits, 54 (7): 1993-2008 (2019)A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET.S. Bailey, J. Han, P. Rigge, R. Lin, E. Chang, H. Mao, Z. Wang, C. Markley, A. Izraelevitz, A. Wang and 21 other author(s). A-SSCC, page 285-288. IEEE, (2018)Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC.B. Keller, M. Cochet, B. Zimmer, Y. Lee, M. Blagojevic, J. Kwak, A. Puggelli, S. Bailey, P. Chiu, D. Dabbelt and 4 other author(s). ESSCIRC, page 269-272. IEEE, (2016)A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.J. Han, E. Chang, S. Bailey, Z. Wang, W. Bae, A. Wang, N. Narevsky, A. Whitcombe, P. Lu, B. Nikolic and 1 other author(s). CICC, page 1-4. IEEE, (2019)A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.B. Keller, M. Cochet, B. Zimmer, J. Kwak, A. Puggelli, Y. Lee, M. Blagojevic, S. Bailey, P. Chiu, D. Dabbelt and 4 other author(s). IEEE J. Solid State Circuits, 52 (7): 1863-1875 (2017)A 21pJ/frame/pixel Imager and 34pJ/frame/pixel Image Processor for a Low-Vision Augmented-Reality Smart Contact Lens.R. Singh, S. Bailey, P. Chang, A. Olyaei, M. Hekmat, and R. Winoto. ISSCC, page 482-484. IEEE, (2021)A 28nm FDSOI 8192-point digital ASIC spectrometer from a Chisel generator.S. Bailey, J. Wright, N. Mehta, R. Hochman, R. Jarnot, V. Milovanovic, D. Werthimer, and B. Nikolic. CICC, page 1-4. IEEE, (2018)

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Disambiguation of "Bailey, Stevo"

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A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.

Please choose a person to relate this publication to

Christopher Bailey

Paul Bailey

Sam Bailey

Jörg Schmidt-Bailey

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Bailey, Stevo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.

Please choose a person to relate this publication to

Christopher Bailey

Paul Bailey

Sam Bailey

Jörg Schmidt-Bailey

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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APA
Chicago
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A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.