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System Level Design of Reconfigurable Systems-on-Chip

, and (Eds.) Springer-Verlag New York, Inc., Secaucus, NJ, USA, (2005)

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Memory accesses reordering for interconnect power reduction in sum-of-products computations., , , , and . IEEE Trans. Signal Process., 50 (11): 2889-2899 (2002)Implementation of Wireless Communications Systems on FPGA-Based Platforms., and . EURASIP J. Embed. Syst., (2007)Power Efficient Hierarchical Scheduling for DSP Transformations., , and . VLSI Design, 14 (2): 203-217 (2002)Υψηλού επιπέδου μέθοδοι μείωσης της κατανάλωσης ενέργειας σε εφαρμογές πολυμέσων. University of Patras, Greece, (2000)National Archive of PhD Theses: oai:10442/31102.Efficient Hardware Looping Units for FPGAs., and . ISVLSI, page 35-40. IEEE Computer Society, (2010)Automatic Generation of Code Analysis Tools: The CastQL Approach., , , and . RWDSL@CGO, page 3:1-3:10. ACM, (2016)Reuse distance analysis for locality optimization in loop-dominated applications., , and . DATE, page 1237-1240. ACM, (2015)Dynamic source code analysis for memory hierarchy optimization in multimedia applications., , , and . DASIP, page 343-344. IEEE, (2013)System Level Design of Complex Hardware Applications Using ImpulseC., , and . ISVLSI, page 473-474. IEEE Computer Society, (2010)A Locality Optimizer for Loop-dominated Applications Based on Reuse Distance Analysis., , , and . ACM Trans. Design Autom. Electr. Syst., 25 (6): 51:1-51:26 (2020)