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W hardware accelerator for binary convolutional neural networks.

A. Bahou, G. Karunaratne, R. Andri, L. Cavigelli, and L. Benini. COOL CHIPS, page 1-3. IEEE Computer Society, (2018)

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Pasan Karunaratne

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Generalized Key-Value Memory to Flexibly Adjust Redundancy in Memory-Augmented Networks.D. Kleyko, G. Karunaratne, J. Rabaey, A. Sebastian, and A. Rahimi. CoRR, (2022)TCNCA: Temporal Convolution Network with Chunked Attention for Scalable Sequence Processing.A. Terzic, M. Hersche, G. Karunaratne, L. Benini, A. Sebastian, and A. Rahimi. CoRR, (2023)Generalized Key-Value Memory to Flexibly Adjust Redundancy in Memory-Augmented Networks.D. Kleyko, G. Karunaratne, J. Rabaey, A. Sebastian, and A. Rahimi. IEEE Trans. Neural Networks Learn. Syst., 34 (12): 10993-10998 (December 2023)In-memory Vector Symbolic Architectures.G. Karunaratne. ETH Zurich, Zürich, Switzerland, (2023)base-search.net (ftethz:oai:www.research-collection.ethz.ch:20.500.11850/625319).Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing.R. Guirado, A. Rahimi, G. Karunaratne, E. Alarcón, A. Sebastian, and S. Abadal. IJCNN, page 1-8. IEEE, (2022)Real-time Language Recognition using Hyperdimensional Computing on Phase-change Memory Array.G. Karunaratne, A. Rahimi, M. Gallo, G. Cherubini, and A. Sebastian. AICAS, page 1. IEEE, (2021)Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH).J. Klein, A. Levisse, G. Ansaloni, D. Atienza, M. Zapater, M. Dazzi, G. Karunaratne, I. Boybat, A. Sebastian, D. Rossi and 12 other author(s). CF, page 191-193. ACM, (2021)Robust High-dimensional Memory-augmented Neural Networks.G. Karunaratne, M. Schmuck, M. Gallo, G. Cherubini, L. Benini, A. Sebastian, and A. Rahimi. CoRR, (2020)HERMES-Core - A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs.R. Khaddam-Aljameh, M. Stanisavljevic, J. Mas, G. Karunaratne, M. Brändli, F. Liu, A. Singh, S. Müller, U. Egger, A. Petropoulos and 14 other author(s). IEEE J. Solid State Circuits, 57 (4): 1027-1038 (2022)Limits of Transformer Language Models on Learning Algorithmic Compositions.J. Thomm, A. Terzic, G. Karunaratne, G. Camposampiero, B. Schölkopf, and A. Rahimi. CoRR, (2024)

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Disambiguation of "Karunaratne, Geethan"

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XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks.

Please choose a person to relate this publication to

Pasan Karunaratne

Other publications of authors with the same name

Disambiguation

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Disambiguation of "Karunaratne, Geethan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks.

Please choose a person to relate this publication to

Pasan Karunaratne

Other publications of authors with the same name

Disambiguation

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URL
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Chicago
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XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks.