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Disambiguation of "Liscidini, Antonio"

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A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS.

, , , and . CICC, page 1-4. IEEE, (2017)

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Antonio Nuzzo

Antonio Galeano

Antonio Souto

Antonio Peter

Antonio Bergua

 

Other publications of authors with the same name

20.9 A 1.92mW filtering transimpedance amplifier for RF current passive mixers., and . ISSCC, page 358-359. IEEE, (2016)A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers., , , and . IEEE J. Solid State Circuits, 53 (3): 681-691 (2018)Low-Power QPSK Transmitter Based on an Injection-Locked Power Amplifier., , and . ESSCIRC, page 134-137. IEEE, (2018)A low-power sub-GHz RF receiver front-end with enhanced blocker tolerance., , and . CICC, page 1-4. IEEE, (2018)A 0.13 μm CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier., , , and . IEEE J. Solid State Circuits, 41 (4): 981-989 (2006)A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO., , , , , and . ISSCC, page 1892-1901. IEEE, (2006)F4: Wireless low-power transceivers for local and wide-area networks., , , , and . ISSCC, page 509-511. IEEE, (2017)Introduction to the Special Issue on the 38th European Solid-State Circuits Conference (ESSCIRC)., and . IEEE J. Solid State Circuits, 48 (7): 1555-1557 (2013)Introduction to the December Special Issue on the 2016 IEEE International Solid-State Circuits Conference., , , , and . IEEE J. Solid State Circuits, 51 (12): 2803-2807 (2016)A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps., , and . IEEE J. Solid State Circuits, 47 (7): 1626-1635 (2012)