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Disambiguation of "Yamada, Tetsuya"

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A 45nm 37.3GOPS/W heterogeneous multi-core SoC.

, , , , , , , , , , , , , , , , , , and . ISSCC, page 100-101. IEEE, (2010)

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Chisaburo Yamada

Tetsuya Takahashi

Osamu Yamada

Hitoshi Yamada

Tetsuya Mizutani

 

Other publications of authors with the same name

Hierarchical power distribution and power management scheme for a single chip mobile processor., , , , , , , , , and 23 other author(s). DAC, page 292-295. ACM, (2006)Application of phased-array antenna technology to the 21 GHz broadcasting satellite for rain-attenuation compensation., , , and . ICC, page 2962-2966. IEEE, (2002)A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation., , , , and . ASP-DAC, page 547-550. IEEE, (2006)On the Computational Power of Binary Decision Diagram with Redundant Variables., and . Formal Methods Syst. Des., 8 (1): 65-89 (1996)Development of processor cores for digital consumer appliances., , , , , , , , , and 2 other author(s). Syst. Comput. Jpn., 37 (3): 10-19 (2006)Hardware support for resource partitioning in real-time embedded systems., , , , , , , , , and 1 other author(s). COOL Chips, page 1-3. IEEE Computer Society, (2013)A 45nm 37.3GOPS/W heterogeneous multi-core SoC., , , , , , , , , and 9 other author(s). ISSCC, page 100-101. IEEE, (2010)Battery-Aware IT Control Method for Effective Battery Use During Power Outage., and . GreenCom, page 565-572. IEEE Computer Society, (2012)A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core., , , , , , , and . IEICE Trans. Electron., 90-C (2): 523-530 (2007)Boundedness of solutions to a parabolic attraction-repulsion chemotaxis system in R2: The attractive dominant case., , and . Appl. Math. Lett., (2021)