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Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding.

, , , , , , , , , , , , , , , and . 3DIC, page 1-4. IEEE, (2011)

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Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding., , , , , , , , , and 6 other author(s). 3DIC, page 1-4. IEEE, (2011)3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps., , , , , , , , , and 9 other author(s). ICICDT, page 1-4. IEEE, (2012)In-line metrology and inspection for process control during 3D stacking of IC's., , , , , , , and . 3DIC, page 1-4. IEEE, (2011)300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications., , , , , , , , , and . 3DIC, page 1-4. IEEE, (2010)Impact of 3D design choices on manufacturing cost., , , , and . 3DIC, page 1-5. IEEE, (2009)Mechanical reliability of Au and Cu wire bonds to Al, Ni/Au and Ni/Pd/Au capped Cu bond pads., , and . Microelectron. Reliab., 46 (8): 1315-1325 (2006)Detection of failure sites by focused ion beam and nano-probing in the interconnect of three-dimensional stacked circuit structures., , , , , and . Microelectron. Reliab., 48 (8-9): 1517-1520 (2008)3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot., , , , , , , , and . Proc. IEEE, 97 (1): 96-107 (2009)3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)., , , , , , , , , and 3 other author(s). 3DIC, page 1-5. IEEE, (2009)