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Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding.

A. Phommahaxay, A. Jourdain, G. Verbinnen, T. Woitke, P. Bisson, M. Gabriel, W. Spiess, A. Guerrero, J. McCutcheon, R. Puligadda, P. Bex, A. den Eede, B. Swinnen, G. Beyer, A. Miller, and E. Beyne. 3DIC, page 1-4. IEEE, (2011)

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Gerald Beyer

Helene Beyer

Alexander Beyer

Susanne Beyer

Erich Beyer

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Reliability challenges for barrier/liner system in high aspect ratio through silicon vias.Y. Li, S. Huylenbroeck, E. Besien, X. Shi, C. Wu, M. Stucchi, G. Beyer, E. Beyne, I. Wolf, and K. Croes. Microelectron. Reliab., 54 (9-10): 1949-1952 (2014)Die to wafer 3D stacking for below 10um pitch microbumps.J. Derakhshandeh, L. Hou, I. Preter, C. Gerets, S. Suhard, V. Dubey, G. Jamieson, F. Inoue, T. Webers, P. Bex and 8 other author(s). 3DIC, page 1-4. IEEE, (2016)Analysis of microbump induced stress effects in 3D stacked IC technologies.A. Ivankovic, G. der Plas, V. Moroz, M. Choi, V. Cherman, A. Mercha, P. Marchal, M. Gonzalez, G. Eneman, W. Zhang and 9 other author(s). 3DIC, page 1-5. IEEE, (2011)Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectrics.S. Kim, L. Peng, A. Miller, G. Beyer, E. Beyne, and C. Lee. 3DIC, page TS7.2.1-TS7.2.4. IEEE, (2015)Extreme wafer thinning optimization for via-last applications.A. Jourdain, J. Vos, F. Inoue, K. Rebibis, A. Miller, G. Beyer, E. Beyne, E. Walsby, J. Patel, O. Ansell and 3 other author(s). 3DIC, page 1-5. IEEE, (2016)In-line metrology and inspection for process control during 3D stacking of IC's.S. Halder, I. Wolf, A. Phommahaxay, A. Miller, M. Maenhoudt, G. Beyer, B. Swinnen, and E. Beyne. 3DIC, page 1-4. IEEE, (2011)Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.A. Veloso, A. Jourdain, D. Radisic, R. Chen, G. Arutchelvan, B. O'Sullivan, H. Arimura, M. Stucchi, A. Keersgieter, M. Hosseini and 34 other author(s). VLSI Technology and Circuits, page 284-285. IEEE, (2022)3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps.W. Guo, G. der Plas, A. Ivankovic, G. Eneman, V. Cherman, B. Wachter, A. Mercha, M. Gonzalez, Y. Civale, A. Redolfi and 9 other author(s). ICICDT, page 1-4. IEEE, (2012)Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN).E. Beyne, A. Jourdain, and G. Beyer. VLSI Technology and Circuits, page 1-2. IEEE, (2023)Process Complexity and Cost Considerations of Multi-Layer Die Stacks.D. Velenis, J. Vos, S. Kim, J. Derakhshandeh, P. Bex, G. Capuz, S. Suhard, K. Rebibis, S. Huylenbroeck, E. Marinissen and 5 other author(s). 3DIC, page 1-6. IEEE, (2019)

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Disambiguation of "Beyer, Gerald"

Please choose a person to relate this publication to

Gerald Beyer

Helene Beyer

Alexander Beyer

Susanne Beyer

Erich Beyer

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Beyer, Gerald"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding.

Please choose a person to relate this publication to

Gerald Beyer

Helene Beyer

Alexander Beyer

Susanne Beyer

Erich Beyer

Other publications of authors with the same name

Disambiguation