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Disambiguation of "Schiavone, Pasquale Davide"

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Always-On 674μ W@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node.

, , , , and . IEEE Trans. Circuits Syst., 67-I (11): 3905-3918 (2020)

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Pablo Pasquale

David Pasquale

Pasquale Pirrone

Pasquale Cardamone

Pasquale Calabrese

 

Other publications of authors with the same name

Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (4): 677-690 (2021)On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification., , , , , and . DFT, page 1-6. IEEE, (2019)Fast and Accurate Multiclass Inference for MI-BCIs Using Large Multiscale Temporal and Spectral Features., , , , , and . EUSIPCO, page 1690-1694. IEEE, (2018)Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores., , , , , and . ISCAS, page 1-5. IEEE, (2021)Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node., , , , and . CoRR, (2020)Performance evaluation of acceleration of convolutional layers on OpenEdgeCGRA., , , , , , and . CoRR, (2024)Motor-Unit Ordering of Blindly-Separated Surface-EMG Signals for Gesture Recognition., , , , , and . SYSINT, volume 546 of Lecture Notes in Networks and Systems, page 518-529. Springer, (2022)sEMG Neural Spikes Reconstruction for Gesture Recognition on a Low-Power Multicore Processor., , , , , , and . BioCAS, page 704-708. IEEE, (2022)X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators., , , , and . CoRR, (2024)An evolutionary approach for test program compaction., , , , and . LATS, page 1-6. IEEE Computer Society, (2015)