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13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications.

T. Song, W. Rim, J. Jung, G. Yang, J. Park, S. Park, K. Baek, S. Baek, S. Oh, J. Jung, S. Kim, G. Kim, J. Kim, Y. Lee, K. Kim, S. Sim, J. Yoon, and K. Choi. ISSCC, page 232-233. IEEE, (2014)

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Rim Nahoui

Rim Abid

Gol Rim

Rim Hjeij

Rim Bahroun

Other publications of authors with the same name

Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM.H. Jeong, J. Park, T. Oh, W. Rim, T. Song, G. Kim, H. Won, and S. Jung. IEEE Trans. Circuits Syst. II Express Briefs, 63-II (11): 1059-1063 (2016)13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications.T. Song, W. Rim, J. Jung, G. Yang, J. Park, S. Park, K. Baek, S. Baek, S. Oh, J. Jung and 8 other author(s). ISSCC, page 232-233. IEEE, (2014)Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_MIN$ Improvement and Energy Saving.H. Jeong, S. Oh, T. Oh, H. Kim, C. Park, W. Rim, T. Song, and S. Jung. IEEE J. Solid State Circuits, 54 (3): 896-906 (2019)A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit.T. Song, H. Kim, W. Rim, H. Jung, C. Park, I. Lee, S. Baek, and J. Jung. IEEE J. Solid State Circuits, 57 (1): 236-244 (2022)Adaptive Clock Generation Technique for Variation-Aware Subthreshold Logics.W. Rim, W. Choi, and J. Park. IEEE Trans. Circuits Syst. II Express Briefs, 59-II (9): 587-591 (2012)24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit.T. Song, W. Rim, H. Kim, K. Cho, T. Kim, T. Lee, G. Bae, D. Kim, S. Kwon, S. Baek and 6 other author(s). ISSCC, page 338-340. IEEE, (2021)Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process.G. Yang, H. Jung, J. Lim, J. Seo, I. Kim, J. Yu, H. You, J. Kong, G. Kim, M. Jeong and 9 other author(s). VLSI Technology and Circuits, page 363-364. IEEE, (2022)3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology.T. Song, H. Jung, G. Yang, H. Tang, H. Kim, D. Seo, H. Kim, W. Rim, S. Baek, S. Baeck and 1 other author(s). CICC, page 1-7. IEEE, (2022)

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Disambiguation of "Rim, Woojin"

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13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications.

Please choose a person to relate this publication to

Rim Nahoui

Rim Abid

Gol Rim

Rim Hjeij

Rim Bahroun

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Rim, Woojin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications.

Please choose a person to relate this publication to

Rim Nahoui

Rim Abid

Gol Rim

Rim Hjeij

Rim Bahroun

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications.