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A Novel Division Algorithm and Architectures for Parallel and Sequential Processing., , , and . Journal of Circuits, Systems, and Computers, 14 (2): 281-296 (2005)Trading Fault-Masking with Performance Overhead for FPGAs., and . ARCS Workshops, VDE-Verlag, (2011)Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic., , , , and . Great Lakes Symposium on VLSI, page 83-88. IEEE Computer Society, (1998)A reusable IP FFT core for DSP applications., , , , , , and . ISCAS (3), page 621-624. IEEE, (2004)Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations., , , , and . ICICDT, page 1-4. IEEE, (2014)On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal., , , and . ISCAS (4), page 334-337. IEEE, (2001)Accuracy of Quasi-Monte Carlo technique in failure probability estimations., , , , and . ICICDT, page 1-4. IEEE, (2016)A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications., , and . ISCAS, IEEE, (2006)Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks., , , , and . PARMA-DITAM@HiPEAC, page 13-16. ACM, (2014)First impressions from detailed brain model simulations on a Xeon/Xeon-Phi node., , , , , and . Conf. Computing Frontiers, page 361-364. ACM, (2016)