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A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.

C. Sudarshan, T. Soliman, J. Lappas, C. Weis, M. Sadi, M. Jung, A. Guntoro, and N. Wehn. IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (2): 367-380 (2022)

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Khalil Tahai

Saoud Asaad Taha

Amr Soliman Ali Soliman

Karin Soliman

Inas Soliman

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Increasing Throughput of In-Memory DNN Accelerators by Flexible Layerwise DNN Approximation.C. la Parra, T. Soliman, A. Guntoro, A. Kumar, and N. Wehn. IEEE Micro, 42 (6): 17-24 (2022)FELIX: A Ferroelectric FET Based Low Power Mixed-Signal In-Memory Architecture for DNN Acceleration.T. Soliman, N. Laleni, T. Kirchner, F. Müller, A. Shrivastava, T. Kämpfe, A. Guntoro, and N. Wehn. ACM Trans. Embed. Comput. Syst., 21 (6): 84:1-84:25 (November 2022)Adaptable Approximation Based on Bit Decomposition for Deep Neural Network Accelerators.T. Soliman, C. la Parra, A. Guntoro, and N. Wehn. AICAS, page 1-4. IEEE, (2021)A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs.C. Sudarshan, T. Soliman, C. la Parra, C. Weis, L. Ecco, M. Jung, N. Wehn, and A. Guntoro. ASP-DAC, page 35-42. ACM, (2021)Fast validation of DRAM protocols with timed petri nets.M. Jung, K. Kraft, T. Soliman, C. Sudarshan, C. Weis, and N. Wehn. MEMSYS, page 133-147. ACM, (2019)Enhancing the Utilization of Dot-Product Engines in Deep Learning Accelerators.T. Soliman, A. Runge, and L. Ecco. IPDPS Workshops, page 840-843. IEEE, (2020)SimPyler: A Compiler-Based Simulation Framework for Machine Learning Accelerators.Y. Braatz, D. Rieber, T. Soliman, and O. Bringmann. ASAP, page 213-220. IEEE, (2023)A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks.T. Soliman, R. Olivo, T. Kirchner, M. Lederer, T. Kämpfe, A. Guntoro, and N. Wehn. SoCC, page 96-101. IEEE, (2020)Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design.C. la Parra, A. El-Yamany, T. Soliman, A. Kumar, N. Wehn, and A. Guntoro. ISCAS, page 1-5. IEEE, (2021)Torwards Variability Immune Scalable FeFET-based Macros for IMC DNN Accelerators.N. Laleni, T. Soliman, C. la Parra, F. Müller, T. Kirchner, A. Guntoro, T. Kämpfe, N. Wehn, and T. Jang. ICECS, page 1-4. IEEE, (2023)

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Disambiguation of "Soliman, Taha"

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A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.

Please choose a person to relate this publication to

Khalil Tahai

Saoud Asaad Taha

Amr Soliman Ali Soliman

Karin Soliman

Inas Soliman

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Soliman, Taha"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.

Please choose a person to relate this publication to

Khalil Tahai

Saoud Asaad Taha

Amr Soliman Ali Soliman

Karin Soliman

Inas Soliman

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.