Author of the publication

A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.

, , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (2): 367-380 (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Increasing Throughput of In-Memory DNN Accelerators by Flexible Layerwise DNN Approximation., , , , and . IEEE Micro, 42 (6): 17-24 (2022)Adaptable Approximation Based on Bit Decomposition for Deep Neural Network Accelerators., , , and . AICAS, page 1-4. IEEE, (2021)A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs., , , , , , , and . ASP-DAC, page 35-42. ACM, (2021)Fast validation of DRAM protocols with timed petri nets., , , , , and . MEMSYS, page 133-147. ACM, (2019)Ultra-low power approximate processing-in-memory acceleration for deep neural networks = Approximative Prozessierung viellagiger neuronaler Netze in Speichermatrizen für Systeme mit ultra-geringer Leistungsaufnahme.. Kaiserslautern University of Technology, Germany, (2022)FELIX: A Ferroelectric FET Based Low Power Mixed-Signal In-Memory Architecture for DNN Acceleration., , , , , , , and . ACM Trans. Embed. Comput. Syst., 21 (6): 84:1-84:25 (November 2022)Enhancing the Utilization of Dot-Product Engines in Deep Learning Accelerators., , and . IPDPS Workshops, page 840-843. IEEE, (2020)SimPyler: A Compiler-Based Simulation Framework for Machine Learning Accelerators., , , and . ASAP, page 213-220. IEEE, (2023)A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks., , , , , , and . SoCC, page 96-101. IEEE, (2020)Neoscope: How Resilient Is My SoC to Workload Churn?, , , and . ISCA, page 1296-1310. ACM, (2025)