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Disambiguation of "Guntoro, Andre"

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A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.

, , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (2): 367-380 (2022)

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Andre Guntoro

Guntoro Thio

Janin Andres

Untersuchungen über Regulationsmechanismen der 11beta-Hydroxysteroid-Dehydrogenase Typ 1. Uni Potsdam, (2008)

Andre Peters

Description and determination of soil hydraulic properties on the laboratory scale. TU Braunschweig, (2008)

Renate Andresen

 

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Efficient FeFET Crossbar Accelerator for Binary Neural Networks., , , , , , , and . ASAP, page 109-112. IEEE, (2020)Exploiting Subword Permutations to Maximize CNN Compute Performance and Efficiency, , , , and . Proceedings - 2023 IEEE 34th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2023, page 61--68. United States, Institute of Electrical and Electronics Engineers Inc., (2023)Funding Information: This work is supported by the German federal ministry of education and research (BMBF), project ZuSE-KI-AVF (grant no. 16ME0062).; 34th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2023 ; Conference date: 19-07-2023 Through 21-07-2023.Online Quantization Adaptation for Fault-Tolerant Neural Network Inference., , , and . SAFECOMP, volume 14181 of Lecture Notes in Computer Science, page 243-256. Springer, (2023)Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling., , , , and . ReCoSoC, page 7-14. Univ. Montpellier II, (2007)A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference., , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (2): 367-380 (2022)A framework for the acoustic simulation of passing vehicles using variable length delay lines., , , and . EURASIP J. Audio Speech Music. Process., 2024 (1): 49 (December 2024)An Efficient Bit-Flip Resilience Optimization Method for Deep Neural Networks., , and . DATE, page 1507-1512. IEEE, (2019)Efficient On-Line Error Detection and Mitigation for Deep Neural Network Accelerators., , and . SAFECOMP, volume 11093 of Lecture Notes in Computer Science, page 205-219. Springer, (2018)High-performance fpga-based floating-point adder with three inputs., and . FPL, page 627-630. IEEE, (2008)Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design., , , , , and . ISCAS, page 1-5. IEEE, (2021)