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Phase noise vs. jitter analysis in continuous-time LP and BP ΣΔ modulators with interferers.

, , , , and . ICECS, page 476-479. IEEE, (2016)

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Design of a high linearity Gm stage for a high speed current mode SAR ADC., , , , and . ICECS, page 136-139. IEEE, (2014)Low power quantizer design in CT Delta Sigma modulators., , , , and . ISCAS, page 1990-1993. IEEE, (2013)A Genetic Algorithm for the Estimation of Nonidealities in Continuous-Time Sigma-Delta Modulators., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (6): 388-392 (2014)A square root unscented Kalman filter for estimating DAC and loopfilter nonidealities in continuous-time sigma-delta modulators., , , , and . ISCAS, page 1159-1162. IEEE, (2014)A power efficient MDAC design with correlated double sampling for a 2-step-flash ADC., , and . ISCAS, page 3138-3141. IEEE, (2012)Concurrent estimation of amplifier nonidealities and excess loop delay in continuous-time sigma-delta modulators., , , and . ISCAS, page 1031-1034. IEEE, (2013)A DAC cell with improved ISI and noise performance using native switching for multi-bit CT Delta Sigma modulators., , , and . ISCAS, page 574-577. IEEE, (2013)Continuous-Time Delta-Sigma ADCs With Improved Interferer Rejection., and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (4): 500-513 (2015)Estimation of Non-Idealities in Sigma-Delta Modulators for Test and Correction Using Unscented Kalman Filters., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (5): 1240-1249 (2015)Phase noise vs. jitter analysis in continuous-time LP and BP ΣΔ modulators with interferers., , , , and . ICECS, page 476-479. IEEE, (2016)