( en | de | ru )

 

Disambiguation of "Wehn, Norbert"

Author of the publication

copydeleteadd this publication to your clipboard
Novel System Simulation Framework for HBM2 FPGA Platforms

, , , , , , , , and . Springer, (2024)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Norbert Wehn

Carl Wehn

Robert Wehn

Arnold Wehn

Joachim Wehn

 

Other publications of authors with the same name

A 506Gbit/s Polar Successive Cancellation List Decoder with CRC., , , , , , and . PIMRC, page 1-7. IEEE, (2020)Low-complexity Computational Units for the Local-SOVA Decoding Algorithm., , , , and . PIMRC, page 1-6. IEEE, (2020)Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes., , , , , and . ISTC, page 1-5. IEEE, (2021)Efficient FeFET Crossbar Accelerator for Binary Neural Networks., , , , , , , and . ASAP, page 109-112. IEEE, (2020)A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference., , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (2): 367-380 (2022)Novel System Simulation Framework for HBM2 FPGA Platforms, , , , , , , , and . Springer, (2024)Fast and Accurate DRAM Simulation: Can we Further Accelerate it?, , , , and . DATE, page 364-369. IEEE, (2020)FeFET versus DRAM based PIM Architectures: A Comparative Study., , , , and . VLSI-SoC, page 1-6. IEEE, (2022)Combined Turbo and Convolutional Decoder Architecture for UMTS Wireless Applications., , , and . SBCCI, page 337-344. IEEE Computer Society, (2002)A Framework for Formal Verification of DRAM Controllers., , , , and . MEMSYS, page 6:1-6:7. ACM, (2022)