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Petaflop Computing for Protein Folding., , , , and . PPSC, (2001)Using Circuits and Systems-Level Research to Drive Nanotechnology., , and . ICCD, page 302-309. IEEE Computer Society, (2004)Logic in Wire: Using Quantum Dots to Implement a Microprocessor., and . Great Lakes Symposium on VLSI, page 118-121. IEEE Computer Society, (1999)A mixed signal architecture for convolutional neural networks., , , , , , and . CoRR, (2018)TFET-based Operational Transconductance Amplifier Design for CNN Systems., , , , , and . ACM Great Lakes Symposium on VLSI, page 277-282. ACM, (2015)Guest Editors' Introduction: Special Issue on Architecture Advances Enabled by Emerging Technologies., , , and . IEEE Des. Test, 36 (3): 5-6 (2019)Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs., , , , , and . IEEE Trans. Emerg. Top. Comput., 5 (3): 340-352 (2017)Computing with ferroelectric FETs: Devices, models, systems, and applications., , , , , , , , , and 9 other author(s). DATE, page 1289-1298. IEEE, (2018)GC-eDRAM design using hybrid FinFET/NC-FinFET., , , , and . ISLPED, page 199-204. ACM, (2020)An Ultra-Dense 2FeFET TCAM Design Based on a Multi-Domain FeFET Model., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (9): 1577-1581 (2019)