Author of the publication

An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver.

, , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (12): 2347-2356 (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An embedded DSP core for wireless communication., , , , and . ISCAS (4), page 524-527. IEEE, (2002)4/2 PAM serial link transmitter with tunable pre-emphasis., , , and . ISCAS (1), page 952-958. IEEE, (2004)An ultra-low voltage hearing aid chip using variable-latency design technique., , , , , and . ISCAS, page 2543-2546. IEEE, (2014)A 12.5 Gbps CMOS input sampler for serial link receiver front end., , and . ISCAS (2), page 1055-1058. IEEE, (2005)A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology., , , , , and . SoCC, page 160-164. IEEE, (2014)Power and area reduction in multi-stage addition using operand segmentation., , , and . VLSI-DAT, page 1-4. IEEE, (2013)Full-digital high throughput design of adaptive decision feedback equalizers using coefficient-lookahead., , , and . ASICON, page 1-4. IEEE, (2015)Novel Programmable FIR Filter Based on Higher Radix Recoding for Low-Power and High-Performance Applications., and . ICASSP (3), page 1473-1476. IEEE, (2007)A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control., , , , , , , , , and 9 other author(s). SoCC, page 197-200. IEEE, (2011)Low-Power Embedded DSP Core for Communication Systems., , , , and . EURASIP J. Adv. Signal Process., 2003 (13): 1355-1370 (2003)