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Design and Characterization of the TERO-PUF on SRAM FPGAs.

, , and . ISVLSI, page 134-139. IEEE Computer Society, (2016)

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Exploration de l'espace de conception des architectures reconfigurables., , and . Technique et Science Informatiques, 25 (7): 921-946 (2006)Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA., , , , and . HASP@ISCA, page 4. ACM, (2013)Communication Costs Driven Design Space Exploration for Reconfigurable Architectures., , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 921-933. Springer, (2003)The Security of ARM TrustZone in a FPGA-Based SoC., , and . IEEE Trans. Computers, 68 (8): 1238-1248 (2019)A Low Cost Alternative Method for Harmonics Estimation in a BIST Context., , , , , , , and . European Test Symposium, page 193-198. IEEE Computer Society, (2006)Contactless transmission of intellectual property data to protect FPGA designs., , and . VLSI-SoC, page 19-24. IEEE, (2015)Complete activation scheme for FPGA-oriented IP cores design protection., , , , , and . FPL, page 1. IEEE, (2017)New paradigms for access control in constrained environments., , , , and . ReCoSoC, page 1-4. IEEE, (2014)Functional Locking Modules for Design Protection of Intellectual Property Cores., and . FCCM, page 233. IEEE Computer Society, (2015)Secure Internal Communication of a Trustzone-Enabled Heterogeneous Soc Lightweight Encryption., , and . FPT, page 239-242. IEEE, (2019)