Author of the publication

Symmetrical ESD trigger and pull-up using BIMOS transistor in advanced CMOS technology.

, , , , , , , and . Microelectron. Reliab., 52 (9-10): 1998-2004 (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Symmetrical ESD trigger and pull-up using BIMOS transistor in advanced CMOS technology., , , , , , , and . Microelectron. Reliab., 52 (9-10): 1998-2004 (2012)Study of the ESD defects impact on ICs reliability., , , , , , , , and . Microelectron. Reliab., 44 (9-11): 1811-1815 (2004)Different Failure signatures of multiple TLP and HBM Stresses in an ESD robust protection structure., , , , , , , , and . Microelectron. Reliab., 45 (9-11): 1415-1420 (2005)TCAD and SPICE modeling help solve ESD protection issues in analog CMOS technology., , , , , , and . Microelectron. Reliab., 43 (1): 71-79 (2003)Low Frequency Noise Measurements for ESD Latent Defect Detection in High Reliability Applications., , , , , , , , and . Microelectron. Reliab., 44 (9-11): 1781-1786 (2004)Application of various optical techniques for ESD defect localization., , , , , , , , , and . Microelectron. Reliab., 46 (9-11): 1563-1568 (2006)BIMOS transistor and its applications in ESD protection in advanced CMOS technology., , , , , , , , and . ICICDT, page 1-4. IEEE, (2012)Simulation, characterization and implementation of a new SCR-based device with a turn-off capability for EOS-immune ESD power supply clamps in advanced CMOS technology nodes., , , , , and . Microelectron. Reliab., (2018)Smart Way to Adjust Schottky Barrier Height in 130 nm BiCMOS Process for sub-THz Applications., , , , , , , and . RWS, page 337-340. IEEE, (2020)