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Maximizing scan pin and bandwidth utilization with a scan routing fabric., , , , , , and . ITC, page 1-10. IEEE, (2017)EDT bandwidth management - Practical scenarios for large SoC designs., , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2013)A Case Study of the Test Development for the 2nd Generation ColdFire® Microprocessors., , , , and . ITC, page 424-432. IEEE Computer Society, (1997)Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (6): 1050-1062 (2015)Conversion of small functional test sets of nonscan blocks to scan patterns., , and . ITC, page 691-700. IEEE Computer Society, (2000)Built-in constraint resolution., , , and . ITC, page 10. IEEE Computer Society, (2005)Implementing 1149.1 on CMOS Microprocessors., , , and . ITC, page 999-1006. IEEE Computer Society, (1992)Toward more efficient scan data bandwidth utilization on modern SOCs., , , , , , and . SoCC, page 64-68. IEEE, (2016)Test Development for Second-Generation ColdFire Microprocessors., , , , and . IEEE Des. Test Comput., 15 (3): 70-76 (1998)The Test Features of the Quad-Core AMD Opteron- Microprocessor., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2008)