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Characterization of Interconnect Fault Effects in SRAM-based FPGAs., , and . DDECS, page 65-68. IEEE, (2023)Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu., , , , , and . SIES, page 1-4. IEEE, (2018)Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation., , , and . Int. J. Reconfigurable Comput., (2023)Reliability-Enhanced High-Level Synthesis using Memory Profiling and Fault Injection., , and . ISIE, page 1363-1370. IEEE, (2019)FIJI: Fault InJection Instrumenter., , , , , and . EURASIP J. Embed. Syst., 2019 (1): 2 (2019)Evaluation of Open-Source Linear Algebra Libraries in Embedded Applications., , , , , , , and . MECO, page 1-6. IEEE, (2019)HLshield: a reliability enhancement framework for high-level synthesis., , and . SIES, page 1-10. IEEE, (2017)Vulnerability analysis of storage elements in HLS-generated designs using high-level profiling., , and . ICSRS, page 190-194. IEEE, (2017)A netlist-level fault-injection tool for FPGAs., , , , and . Elektrotech. Informationstechnik, 132 (6): 274-281 (2015)Evaluation of Open-Source Linear Algebra Libraries targeting ARM and RISC-V Architectures., , , and . FedCSIS, volume 21 of Annals of Computer Science and Information Systems, page 663-672. (2020)