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Warehouse-scale video acceleration: co-design and deployment in the wild., , , , , , , , , and 42 other author(s). ASPLOS, page 600-615. ACM, (2021)In-Datacenter Performance Analysis of a Tensor Processing Unit., , , , , , , , , and 66 other author(s). ISCA, page 1-12. ACM, (2017)In-Datacenter Performance Analysis of a Tensor Processing Unit., , , , , , , , , and 64 other author(s). CoRR, (2017)A simultaneous routing tree construction and fanout optimization algorithm., , and . ICCAD, page 625-630. ACM / IEEE Computer Society, (1998)MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood Search., , and . DAC, page 472-478. ACM Press, (1999)A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement Together., , and . DAC, page 128-134. ACM Press, (1998)An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits., , and . ASP-DAC, page 295-300. IEEE, (1998)Hierarchical buffered routing tree generation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (5): 554-567 (2002)An exact solution to simultaneous technology mapping and linear placement problem., , and . ICCAD, page 671-675. IEEE Computer Society / ACM, (1997)An integrated logical and physical design flow for deep submicron circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (9): 1305-1315 (1999)