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Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C.

, , , and . HPEC, page 1-7. IEEE, (2017)

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Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization., , and . IPCCC, page 372-379. IEEE Computer Society, (2007)MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams., , , , , and . TACO, 16 (4): 35:1-35:26 (2020)A statistical performance model of the opteron processor., , and . SIGMETRICS Perform. Evaluation Rev., 38 (4): 75-80 (2011)Exploring Chapel Productivity Using Some Graph Algorithms., , , , , and . IPDPS Workshops, page 672. IEEE, (2020)StAdHyTM: A Statically Adaptive Hybrid Transactional Memory: A scalability study on large parallel graphs., , and . CCWC, page 1-7. IEEE, (2017)An Idealistic Neuro-PPM Branch Predictor., , , , and . J. Instruction-Level Parallelism, (2007)Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C., , , and . HPEC, page 1-7. IEEE, (2017)Extending Moore's Law via Computationally Error-Tolerant Computing., , , , , , and . TACO, 15 (1): 8:1-8:27 (2018)Toward reducing processor simulation time via dynamic reduction of microarchitecture complexity., , and . SIGMETRICS, page 252-253. ACM, (2002)DyAdHyTM: A Low Overhead Dynamically Adaptive Hybrid Transactional Memory on Big Data Graphs., , and . CoRR, (2017)