Author of the publication

Mirage cores: the illusion of many out-of-order cores using in-order hardware.

, , , and . MICRO, page 745-758. ACM, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration., , , , , , and . ISSCC, page 224-226. IEEE, (2019)Quality-of-Service for a High-Radix Switch., , , , , , and . DAC, page 163:1-163:6. ACM, (2014)Parallel Automata Processor., and . ISCA, page 600-612. ACM, (2017)BitSET: Bit-Serial Early Termination for Computation Reduction in Convolutional Neural Networks., , , , and . ACM Trans. Embed. Comput. Syst., 22 (5s): 98:1-98:24 (October 2023)Hardware-friendly User-specific Machine Learning for Edge Devices., , and . ACM Trans. Embed. Comput. Syst., 21 (5): 62:1-62:29 (September 2022)Duality cache for data parallel acceleration., , and . ISCA, page 397-410. ACM, (2019)Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors., , , and . HPCA, page 313-324. IEEE Computer Society, (2017)XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems., , , , , , , , and . PACT, page 75-86. ACM, (2012)Getting in control of your control flow with control-data isolation., , , and . CGO, page 79-90. IEEE Computer Society, (2015)Cache automaton., , , , , and . MICRO, page 259-272. ACM, (2017)