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A UML Based System Level Failure Rate Assessment Technique for SoC Designs., , , and . VTS, page 243-248. IEEE Computer Society, (2007)Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips., , , , and . VLSI Design, page 157-162. IEEE Computer Society, (2009)Enhanced TED: A New Data Structure for RTL Verification., , , and . VLSI Design, page 481-486. IEEE Computer Society, (2008)Optimizing Data-Center TCO with Scale-Out Processors., , , , , and . IEEE Micro, 32 (5): 52-63 (2012)AxBench: A Benchmark Suite for Approximate Computing Across the System Stack, , , and . (2016)Single-Event Transient Analysis in High Speed Circuits., , , , and . ISED, page 112-117. IEEE Computer Society, (2011)Domino Temporal Data Prefetcher., , and . HPCA, page 131-142. IEEE Computer Society, (2018)TED+: a data structure for microprocessor verification., , , , and . ASP-DAC, page 567-572. ACM Press, (2005)Scale-Out Processors & Energy Efficiency., , , , and . CoRR, (2018)Die-Stacked DRAM: Memory, Cache, or MemCache?, , , and . CoRR, (2018)