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The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.

E. Fluhr, S. Baumgartner, D. Boerstler, J. Bulzacchelli, T. Diemoz, D. Dreps, G. English, J. Friedrich, A. Gattiker, T. Gloekler, C. Gonzalez, J. Hibbeler, K. Jenkins, Y. Kim, P. Muench, R. Nett, J. Paredes, J. Pille, D. Plass, P. Restle, R. Robertazzi, D. Shan, D. Siljenberg, M. Sperling, K. Stawiasz, G. Still, Z. Deniz, J. Warnock, G. Wiedemeier, and V. Zyuban. IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)

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Gerhard Plass

Helmut Plaß

Volker Plass

Roland Plass

Stefan Plaß

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Design of the Power6 Microprocessor.J. Friedrich, B. McCredie, N. James, B. Huott, B. Curran, E. Fluhr, G. Mittal, E. Chan, Y. Chan, D. Plass and 7 other author(s). ISSCC, page 96-97. IEEE, (2007)5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.E. Fluhr, J. Friedrich, D. Dreps, V. Zyuban, G. Still, C. Gonzalez, A. Hall, D. Hogenmiller, F. Malgioglio, R. Nett and 10 other author(s). ISSCC, page 96-97. IEEE, (2014)IBM POWER8 circuit design and energy optimization.V. Zyuban, J. Friedrich, D. Dreps, J. Pille, D. Plass, P. Restle, Z. Deniz, M. Ziegler, S. Chu, M. Islam and 13 other author(s). IBM J. Res. Dev., (2015)The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.E. Fluhr, S. Baumgartner, D. Boerstler, J. Bulzacchelli, T. Diemoz, D. Dreps, G. English, J. Friedrich, A. Gattiker, T. Gloekler and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)5.5GHz system z microprocessor and multi-chip module.J. Warnock, Y. Chan, H. Harrer, D. Rude, R. Puri, S. Carey, G. Salem, G. Mayer, Y. Chan, M. Mayo and 13 other author(s). ISSCC, page 46-47. IEEE, (2013)3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4.C. Gonzalez, E. Fluhr, D. Dreps, D. Hogenmiller, R. Rao, J. Paredes, M. Floyd, M. Sperling, R. Kruse, V. Ramadurai and 4 other author(s). ISSCC, page 50-51. IEEE, (2017)Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics.R. Joshi, S. Mukhopadhyay, D. Plass, Y. Chan, C. Chuang, and Y. Tan. IEEE J. Solid State Circuits, 44 (3): 965-976 (2009)IBM POWER6 SRAM arrays.D. Plass, and Y. Chan. IBM J. Res. Dev., 51 (6): 747-756 (2007)A 5.2GHz microprocessor chip for the IBM zEnterprise™ system.J. Warnock, Y. Chan, W. Huott, S. Carey, M. Fee, H. Wen, M. Saccamango, F. Malgioglio, P. Meaney, D. Plass and 17 other author(s). ISSCC, page 70-72. IEEE, (2011)17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access.G. Fredeman, D. Plass, A. Mathews, K. Reyer, T. Knips, T. Miller, E. Gerhard, D. Kannambadi, C. Paone, D. Lee and 4 other author(s). ISSCC, page 1-3. IEEE, (2015)

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Disambiguation of "Plass, Donald W."

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The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.

Please choose a person to relate this publication to

Gerhard Plass

Helmut Plaß

Volker Plass

Roland Plass

Stefan Plaß

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Plass, Donald W."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.

Please choose a person to relate this publication to

Gerhard Plass

Helmut Plaß

Volker Plass

Roland Plass

Stefan Plaß

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.