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Disambiguation of "Stawiasz, Kevin"

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The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)

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Alexander Ali Kevin

Kevin Thurley

Kevin Niwek

Kevin Niwek

Kevin Reddig

 

Other publications of authors with the same name

Designing a Testable System on a Chip., , , , , , , , , and 5 other author(s). VTS, page 2-7. IEEE Computer Society, (1998)Experimental measurement of a novel power gating structure with intermediate power saving mode., , , and . ISLPED, page 20-25. ACM, (2004)Performance impact of through-silicon vias (TSVs) in three-dimensional technology measured by SRAM ring oscillators., , , and . ESSCIRC, page 419-422. IEEE, (2013)Analyzing path delays for accelerated testing of logic chips., , , , , , , and . IRPS, page 6. IEEE, (2015)SOI FinFET soft error upset susceptibility and analysis., , , , , , , , and . IRPS, page 4. IEEE, (2015)High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor., , , , , , and . VTS, page 234-238. IEEE Computer Society, (1998)A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing., , , , , , , and . IEEE J. Solid State Circuits, 43 (4): 946-955 (2008)The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (7): 586-590 (2007)5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor., , , , , , , , , and 5 other author(s). ISSCC, page 98-99. IEEE, (2014)