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At-speed scan test with low switching activity., , , and . VTS, page 177-182. IEEE Computer Society, (2010)Minimal area test points for deterministic patterns., , , , , and . ITC, page 1-7. IEEE, (2016)Test point insertion in hybrid test compression/LBIST architectures., , , , and . ITC, page 1-10. IEEE, (2016)Isometric test compression with low toggling activity., , , , , , , and . ITC, page 1-7. IEEE Computer Society, (2014)Design for low test pattern counts., , , , , , and . DAC, page 136:1-136:6. ACM, (2015)An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits., and . DSD, page 619-625. IEEE Computer Society, (2007)Test Time and Area Optimized BrST Scheme for Automotive ICs., , , , , , , , , and . ITC, page 1-10. IEEE, (2019)Embedded Deterministic Test Points., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (10): 2949-2961 (2017)Isometric Test Data Compression., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (11): 1847-1859 (2015)Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating., , , and . Asian Test Symposium, page 267-272. IEEE Computer Society, (2011)