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Hysteresis in electronic circuits: A circuit theorist's perspective.

, and . I. J. Circuit Theory and Applications, 19 (5): 471-515 (1991)

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Estimating the locking range of analog dividers through a phase-domain macromodel., , , and . ISCAS, page 1535-1538. IEEE, (2010)Comments on "folding of phase noise spectra in charge-pump phase-locked loops induced by frequency division"., , and . ICECS, page 612-615. IEEE, (2016)First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converter., , and . ICECS, page 41-44. IEEE, (2010)An equation for Generating Chaos and its monolithic Implementation., , and . Int. J. Bifurc. Chaos, 12 (12): 2885-2895 (2002)A CMOS Injection-Locked Frequency Divider Optimized for Divide-by-Two and Divide-by-Three Operation., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (12): 3126-3135 (2013)MMSE Estimator for Linearized Analysis and SNR of ADCs Tested with Sinusoidal Inputs., and . PRIME, page 161-164. IEEE, (2023)A novel dual-loop multi-phase frequency synthesizer., , and . ECCTD, page 567-570. IEEE, (2007)Comments on the effectiveness of the Szabo and Kolumban solution to false lock in sampling PLL frequency synthesizer., and . ECCTD, page 413-416. IEEE, (2005)Design equations and baseband model for double-sampling phase-locked loop., , and . ICECS, page 895-898. IEEE, (1999)Comparison of DTC-Related Spurs in Fractional-N Digital PLLs with MASH-and-ENOP-based Divider Controllers., and . ICECS, page 1-5. IEEE, (2023)