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Disambiguation of "Banerjee, Kaustav"

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Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (6): 849-861 (2005)

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Kaustav Nandy

Abhishek Banerjee

Prabuddha Banerjee

Mita Banerjee

Nandakishore Banerjee

 

Other publications of authors with the same name

On Thermal Effects in Deep Sub-Micron VLSI Interconnects., , , and . DAC, page 885-891. ACM Press, (1999)Are carbon nanotubes the future of VLSI interconnections?, and . DAC, page 809-814. ACM, (2006)A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates., , and . DAC, page 977-982. ACM, (2006)Performance analysis and technology of 3-D ICs., , , and . SLIP, page 85-90. ACM, (2000)Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (6): 823-836 (2004)Analysis of on-chip inductance effects for distributed RLC interconnects., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (8): 904-915 (2002)A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates., and . IEEE Trans. Very Large Scale Integr. Syst., 18 (11): 1567-1577 (2010)Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs., , and . IEEE Des. Test Comput., 27 (4): 20-31 (2010)Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs., , and . CICC, page 233-236. IEEE, (2001)A fast analytical technique for estimating the bounds of on-chip clock wire inductance., , , and . CICC, page 241-244. IEEE, (2001)