( en | de | ru )

 

Disambiguation of "Goossens, Kees"

Author of the publication

copydeleteadd this publication to your clipboard
A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems.

, , , , and . DATE, page 193-198. ACM, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Brigitte Kees

Brigitte Kees

Alain Goossens

Sabine Goossens

Heinrich Goossens

 

Other publications of authors with the same name

A unified execution model for multiple computation models of streaming applications on a composable MPSoC., , and . J. Syst. Archit., 59 (10-C): 1032-1046 (2013)Time synchronization for an emulated CAN device on a Multi-Processor System on Chip., , , and . Microprocess. Microsystems, (2017)Topology Management and TSCH Scheduling for Low-Latency Convergecast in In-Vehicle WSNs., , , and . IEEE Trans. Ind. Informatics, 15 (2): 1082-1093 (2019)A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic., , and . VLSI Design, (2007)Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism., , , , and . IET Comput. Digit. Tech., 1 (3): 197-206 (2007)Composable local memory organisation for streaming applications on embedded MPSoCs., , , , , and . Conf. Computing Frontiers, page 23. ACM, (2011)A Distributed Safety Mechanism using Middleware and Hypervisors for Autonomous Vehicles., , , , , , , , and . DATE, page 1175-1180. IEEE, (2020)Maximizing the Number of Good Dies for Streaming Applications in NoC-Based MPSoCs Under Process Variation., , , and . ACM Trans. Embed. Comput. Syst., 14 (4): 83:1-83:26 (2015)Networks on chips editorial., and . IET Comput. Digit. Tech., 3 (5): 395-397 (2009)C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems., , , , , , , and . Des. Autom. Embed. Syst., 7 (3): 233-270 (2002)