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Disambiguation of "Gürkaynak, Frank K."

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Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS.

, , , , , and . CS2@HiPEAC, page 19-24. ACM, (2017)

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Erdal Gürkaynak

Ethem Yalç Gürkaynak

Frank K Peter

Frank K Wilhelm-Mauch

Aman K K Bhasin

 

Other publications of authors with the same name

High speed ASIC implementations of leakage-resilient cryptography., , , , , and . DATE, page 1259-1264. IEEE, (2018)A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic., , and . VLSI Design, 11 (2): 115-128 (2000)Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture., , and . IACR Cryptology ePrint Archive, (2012)A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime., , and . I. J. Circuit Theory and Applications, 37 (2): 203-220 (2009)Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density., , , , and . ACM Great Lakes Symposium on VLSI, page 204-207. ACM, (2007)A 2 Gb/s balanced AES crypto-chip implementation., , , , , , and . ACM Great Lakes Symposium on VLSI, page 39-44. ACM, (2004)A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range., , , , , and . ESSCIRC, page 263-266. IEEE, (2021)PetaOps/W edge-AI $\mu$ Processors: Myth or reality?, , , , , , , , , and 18 other author(s). DATE, page 1-6. IEEE, (2023)The ECSEL FRACTAL Project: A Cognitive Fractal and Secure edge based on a unique Open-Safe-Reliable-Low Power Hardware Platform., , , , , , , , , and 1 other author(s). DSD, page 393-400. IEEE, (2020)A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets., , , and . CoRR, (2018)