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Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS.

, , , , , and . CS2@HiPEAC, page 19-24. ACM, (2017)

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HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment., , , and . CoRR, (2020)Implementation aspects of the DPA-resistant logic style MDPL., and . ISCAS, IEEE, (2006)Systematic Classification of Side-Channel Attacks: A Case Study for Mobile Devices., , , and . IEEE Commun. Surv. Tutorials, 20 (1): 465-488 (2018)Meltdown., , , , , , , , , and . CoRR, (2018)Exploiting Data-Usage Statistics for Website Fingerprinting Attacks on Android., , , and . WISEC, page 49-60. ACM, (2016)One for All - All for One: Unifying Standard DPA Attacks., , and . IACR Cryptology ePrint Archive, (2009)Side-Channel Plaintext-Recovery Attacks on Leakage-Resilient Encryption., , and . IACR Cryptology ePrint Archive, (2016)Counteracting Power Analysis Attacks by Masking., and . Secure Integrated Circuits and Systems, Springer, (2010)Exploiting the Difference of Side-Channel Leakages., , , , and . COSADE, volume 7275 of Lecture Notes in Computer Science, page 1-16. Springer, (2012)Protecting the Control Flow of Embedded Processors against Fault Attacks., , and . CARDIS, volume 9514 of Lecture Notes in Computer Science, page 161-176. Springer, (2015)