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Disambiguation of "Mehra, Rajesh"

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FPGA-Based Design of High-Speed CIC Decimator for Wireless Applications

. IJACSA - International Journal of Advanced Computer Science and Applications, 2 (5): 59--62 (2011)

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Rajesh Saiju

Hybrid Power System Modelling - Simulation and Energy Management Unit Development. Uni Kassel, (2008)

Rajesh Chitta

Rajesh Saiju

Rajesh Narasimha

Rajesh Kolli

 

Other publications of authors with the same name

High Speed and Area Efficient 2D DWT Processor based Image Compression" Signal & Image Processing, and . CoRR, (2011)FPGA Based Design of High Performance Decimator using DALUT Algorithm, and . International Journal on Signal & Image Processing, 1 (2): 5 (July 2010)Optimised CNN in conjunction with efficient pooling strategy for the multi-classification of breast cancer., , and . IET Image Process., 15 (4): 936-946 (2021)Conventional Machine Learning and Deep Learning Approach for Multi-Classification of Breast Cancer Histopathology Images - a Comparative Insight., and . J. Digit. Imaging, 33 (3): 632-654 (2020)Re-configurable optimized area CTC codec for wireless applications., and . ICACCI, page 2549-2553. IEEE, (2014)Effect of layer-wise fine-tuning in magnification-dependent classification of breast cancer histopathological image., and . Vis. Comput., 36 (9): 1755-1769 (2020)Breast cancer histology images classification: Training from scratch or transfer learning?, and . ICT Express, 4 (4): 247-254 (2018)Low-power and high-speed 13T SRAM cell using FinFETs., and . IET Circuits Devices Syst., 11 (3): 250-255 (2017)FPGA-Based Design of High-Speed CIC Decimator for Wireless Applications. IJACSA - International Journal of Advanced Computer Science and Applications, 2 (5): 59--62 (2011)Ultra Low Power, Trimless and Resistor-less Bandgap Voltage Reference., , and . ICIIS, page 292-296. IEEE, (2018)