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Disambiguation of "Endoh, Tetsuo"

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Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.

, , , , , , , , , , , , , and . ISSCC, page 194-195. IEEE, (2013)

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Tetsuo Morino

Tetsuo Kishimoto

 

Other publications of authors with the same name

Nonvolatile logic and memory devices based on spintronics.. ISCAS, page 13-16. IEEE, (2015)Neuromorphic processor-oriented hybrid Q-format multiplication with adaptive quantization for tiny YOLO3., , and . Neural Comput. Appl., 35 (15): 11013-11041 (May 2023)A High Output Resistance 1.2-V VDD Current Mirror with Deep Submicron Vertical MOSFETs., and . IEICE Trans. Electron., 97-C (5): 423-430 (2014)The Optimum Physical Targets of the 3-Dimensional Vertical FG NAND Flash Memory Cell Arrays with the Extended Sidewall Control Gate (ESCG) Structure., and . IEICE Trans. Electron., 94-C (5): 686-692 (2011)Impact of Floating Body Type DRAM with the Vertical MOSFET., and . IEICE Trans. Electron., 94-C (5): 705-711 (2011)Evaluation of 1/f Noise Characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET with 65 nm CMOS Process., , and . IEICE Trans. Electron., 94-C (5): 724-729 (2011)Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT., , , , and . IEEE Trans. Ind. Informatics, 18 (5): 3055-3065 (2022)A novel memory test system with an electromagnet for STT-MRAM testing., , , , , , and . NVMTS, page 1-4. IEEE, (2019)A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing., , , , , , , , , and 5 other author(s). ISCAS, page 1588-1591. IEEE, (2014)A compact and low power logic design for multi-pillar vertical MOSFETs., and . ISCAS, page 309-312. IEEE, (2010)