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Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS.

, , , , , , and . Proc. IEEE, 96 (2): 343-365 (2008)

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New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm., and . ISQED, page 425-430. IEEE, (2011)Can Subthreshold and Near-Threshold Circuits Go Mainstream?, and . IEEE Micro, 30 (4): 80-85 (2010)Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers., , , and . DAC, page 138-143. ACM, (2010)A charge pump based receiver circuit for voltage scaled interconnect., , and . ISLPED, page 327-332. ACM, (2012)Serial sub-threshold circuits for ultra-low-power systems., and . ISLPED, page 27-32. ACM, (2009)Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design., , , and . ICCD, page 491-497. IEEE Computer Society, (2009)A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs., , , , and . ISQED, page 1-8. IEEE, (2014)A 745pA Hybrid Asynchronous Binary-Searching and Synchronous Linear-Searching Digital LDO with 3.8×105 Dynamic Load Range, 99.99% Current Efficiency, and 2mV Output Voltage Ripple., and . ISSCC, page 232-234. IEEE, (2019)Ultra-low power wireless SoCs enabling a batteryless IoT., and . Hot Chips Symposium, page 1-45. IEEE, (2015)A 4.4 nW lossless sensor data compression accelerator for 2.9x system power reduction in wireless body sensors., , , , , , and . MWSCAS, page 1041-1044. IEEE, (2017)