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PMTJ Temperature Sensor Utilizing VCMA., and . ISCAS, page 1-5. IEEE, (2019)Exploiting the on-chip inductance in high-speed clock distribution networks, , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (6): 963--973 (December 2001)On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits., , , and . SoCC, page 309-312. IEEE, (2005)Test point insertion for RSFQ circuits., and . ISCAS, page 1-4. IEEE, (2017)Behavioral Verilog-A Model of Superconductor-Ferromagnetic Transistor., and . ISCAS, page 1-5. IEEE, (2018)Link breaking methodology: mitigating noise within power networks., and . ACM Great Lakes Symposium on VLSI, page 129-134. ACM, (2012)Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling., , , , , and . ICECS, page 1021-1025. IEEE, (2001)Transient power in CMOS gates driving LC transmission lines., , and . ICECS, page 337-340. IEEE, (1998)A repeater timing model and insertion algorithm to reduce delay in RC tree structures., and . ICECS, page 67-70. IEEE, (1998)Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime., , , , , and . ICCD, page 527-534. IEEE Computer Society, (2015)