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Implementation of a SPIHT coprocessor: memory issues and hardware implications.

, , , and . ICIP (2), page 587-590. IEEE, (2003)

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FPGA implementation of a reconfigurable SPIHT coprocessor., , , and . ISSPA (2), page 605-606. IEEE, (2003)0-7803-7946-2.Design and implementation of phase correlation based motion estimator., , and . SoCC, page 291-294. IEEE, (2005)A reconfigurable, power-scalable rake receiver IP for W-CDMA., , , , and . ASP-DAC, page 499-502. ACM, (2003)A Power-Scalable Motion Estimation Architecture for Energy Constrained Applications., , , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 712-721. Springer, (2003)Design of a Power Conscious, Customizable CDMA Receiver., , , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 1028-1031. Springer, (2003)Reconfigurable DSP IP for multimedia applications., , , , and . ICASSP, page 4179. IEEE, (2002)Reconfigurable VLSI architectures for multimedia applications.. Polytechnic University of Turin, Italy, (2004)A new approach to compress the configuration information of programmable devices., , , , , and . DATE Designers' Forum, page 48-51. European Design and Automation Association, Leuven, Belgium, (2006)Interconnection framework for high-throughput, flexible LDPC decoders., , , , and . DATE Designers' Forum, page 124-129. European Design and Automation Association, Leuven, Belgium, (2006)Real-time implementation of a time-frequency analysis scheme., , , , , , and . ACM Great Lakes Symposium on VLSI, page 180-183. ACM, (2007)