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Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance.

, , , and . ICCAD, page 730-734. IEEE Computer Society, (2007)

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Process variation tolerant SRAM array for ultra low voltage applications., , , and . DAC, page 108-113. ACM, (2008)IMPACT: imprecise adders for low-power approximate computing., , , , and . ISLPED, page 409-414. IEEE/ACM, (2011)Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation., , and . IEEE J. Solid State Circuits, 45 (2): 401-410 (2010)System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (12): 3468-3476 (2016)On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (2): 270-280 (2010)Layout-aware optimization of stt mrams., , , and . DATE, page 1455-1458. IEEE, (2012)Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture., , , , and . DAC, page 492-497. ACM, (2012)A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS., , , and . ISSCC, page 388-389. IEEE, (2008)NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?, , , and . ASP-DAC, page 726-731. IEEE, (2008)Memory-based embedded digital ATE., , , and . VTS, page 266-271. IEEE Computer Society, (2011)