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Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs.

C. Ding, A. Ren, G. Yuan, X. Ma, J. Li, N. Liu, B. Yuan, and Y. Wang. ACM Great Lakes Symposium on VLSI, page 353-358. ACM, (2018)

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Ao Shen

Rong Ao

Rafik Aouane

Saïd Aouada

Nasreddine Aoumeur

Other publications of authors with the same name

ADMM-NN: An Algorithm-Hardware Co-Design Framework of DNNs Using Alternating Direction Methods of Multipliers.A. Ren, T. Zhang, S. Ye, J. Li, W. Xu, X. Qian, X. Lin, and Y. Wang. ASPLOS, page 925-938. ACM, (2019)Design of high-speed low-power polar BP decoder using emerging technologies.A. Ren, B. Yuan, and Y. Wang. SoCC, page 312-316. IEEE, (2016)Deep Reinforcement Learning: Framework, Applications, and Embedded Implementations.H. Li, T. Wei, A. Ren, Q. Zhu, and Y. Wang. CoRR, (2017)Flexible Clustered Federated Learning for Client-Level Data Distribution Shift.M. Duan, D. Liu, X. Ji, Y. Wu, L. Liang, X. Chen, Y. Tan, and A. Ren. IEEE Trans. Parallel Distributed Syst., 33 (11): 2661-2674 (2022)FedMDS: An Efficient Model Discrepancy-Aware Semi-Asynchronous Clustered Federated Learning Framework.Y. Zhang, D. Liu, M. Duan, L. Li, X. Chen, A. Ren, Y. Tan, and C. Wang. IEEE Trans. Parallel Distributed Syst., 34 (3): 1007-1019 (March 2023)Optimizing the Incremental Update Mechanism by Inlaying File Indexes on Flash Storage.R. Lei, X. Chen, D. Liu, C. Song, Y. Tan, and A. Ren. NVMSA, page 56-61. IEEE, (2023)A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture.J. Yue, R. Liu, W. Sun, Z. Yuan, Z. Wang, Y. Tu, Y. Chen, A. Ren, Y. Wang, M. Chang and 3 other author(s). ISSCC, page 138-140. IEEE, (2019)A Majority Logic Synthesis Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits.R. Cai, O. Chen, A. Ren, N. Liu, C. Ding, N. Yoshikawa, and Y. Wang. ACM Great Lakes Symposium on VLSI, page 189-194. ACM, (2019)HBP: Hierarchically Balanced Pruning and Accelerator Co-Design for Efficient DNN Inference.A. Ren, Y. Wang, T. Zhang, J. Shi, D. Liu, X. Chen, Y. Tan, and Y. Xie. DAC, page 1-6. IEEE, (2023)Optimizing the Performance of NDP Operations by Retrieving File Semantics in Storage.L. Li, X. Chen, J. Li, J. Wang, D. Liu, Y. Tan, and A. Ren. DAC, page 1-6. IEEE, (2023)

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Disambiguation of "Ren, Ao"

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Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs.

Please choose a person to relate this publication to

Ao Shen

Rong Ao

Rafik Aouane

Saïd Aouada

Nasreddine Aoumeur

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ren, Ao"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs.

Please choose a person to relate this publication to

Ao Shen

Rong Ao

Rafik Aouane

Saïd Aouada

Nasreddine Aoumeur

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs.