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Low Power Design Bi – Directional Shift Register By using GDI Technique

, , and . International Journal on Recent and Innovation Trends in Computing and Communication, 3 (4): 2367--2373 (April 2015)
DOI: 10.17762/ijritcc2321-8169.1504128

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Low Power Design Bi – Directional Shift Register By using GDI Technique, , and . International Journal on Recent and Innovation Trends in Computing and Communication, 3 (4): 2367--2373 (April 2015)Design and Verification of Cache Memory Decoder for High Speed Multicore Processor., , and . ICETET, page 770-775. IEEE Computer Society, (2010)Design and Verification of Cache Memory Decoder for High Speed Multicore Processor., , and . ICETET, page 770-775. IEEE Computer Society, (2010)