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Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits., , and . IEEE Trans. Computers, 44 (5): 724-728 (1995)Early Analysis of Soft Error Effects for Aerospace Applications Using Probabilistic Model Checking., , , and . FTSCS, volume 419 of Communications in Computer and Information Science, page 54-70. Springer, (2013)A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits., , and . IEEE Trans. Computers, 43 (6): 687-698 (1994)High-Speed Decoders for Polar Codes, , and . Springer, (2017)On Delay Faults Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiations., , , , and . CoRR, (2014)Circuit Level Modeling of Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiation., , , and . CoRR, (2015)Replacing IDDQ Testing: With Variance Reduction.. J. Electron. Test., 19 (3): 325-340 (2003)Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors., , and . J. Electron. Test., 28 (2): 229-242 (2012)Diagnosis Method Using DeltaIDDQ Probabilistic Signatures: Theory and Results.. J. Electron. Test., 16 (4): 339-353 (2000)CDelta IDDQ : Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation., and . IEEE Trans. Very Large Scale Integr. Syst., 19 (1): 130-141 (2011)