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The future of logic synthesis and physical design in deep-submicron process geometries., , and . ISPD, page 218-224. ACM, (1997)On the Temporal Equivalence of Sequential Circuits., , , and . DAC, page 405-409. IEEE Computer Society Press, (1992)Advances in Computation of the Maximum of a Set of Gaussian Random Variables., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (8): 1522-1533 (2007)An Efficient External-Memory Implementation of Region Query with Application to Area Routing., , and . ICCD, page 36-41. IEEE Computer Society, (2002)Timing Analysis with Crosstalk as Fixpoints on Complete Lattice., , and . DAC, page 714-719. ACM, (2001)Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables., and . VLSI Design, page 989-994. IEEE Computer Society, (2004)Statistical gate sizing for timing yield optimization., , and . ICCAD, page 1037-1041. IEEE Computer Society, (2005)Emerging markets: design goes global., , , , , , and . DAC, page 195. ACM, (2003)Logic Synthesis for Programmable Gate Arrays., , , , and . DAC, page 620-625. IEEE Computer Society Press, (1990)Statistical Timing Yield Optimization by Gate Sizing., , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (10): 1140-1146 (2006)