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Disambiguation of "Tran, Xuan-Tu"

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An Asynchronous Power Aware and Adaptive NoC Based Circuit.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 44 (4): 1167-1177 (2009)

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Tran vu Tu

Tran xuan Nam

Tran xuan Hoai

Xuan-Hoai Tran

Tran xuan Hoai

 

Other publications of authors with the same name

A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems., , , and . IEEE Access, (2020)An In-Situ Dynamic Quantization With 3D Stacking Synaptic Memory for Power-Aware Neuromorphic Architecture., , , and . IEEE Access, (2023)A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (9): 3182-3186 (2021)An Asynchronous Power Aware and Adaptive NoC Based Circuit., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 44 (4): 1167-1177 (2009)A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization., , and . APCCAS, page 33-36. IEEE, (2019)A proposal for enhancing training speed in deep learning models based on memory activity survey., , , , , and . IEICE Electron. Express, 18 (15): 20210252 (2021)Low-cost Low-Power Implementation of Binary Edwards Curve for Secure Passive RFID Tags., , , , and . MCSoC, page 494-500. IEEE, (2023)An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks., , , and . SoCC, page 144-149. IEEE, (2019)Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications., , , , and . ICICDT, page 1-4. IEEE, (2016)AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (12): 3281-3290 (2017)